ARM Assembly – Why AAPCS Requires SP to Be 8-Byte Aligned

abiarmassemblycalling-conventionstack-pointer

Since this is a recurring topic, I'm putting up a question about it.

According to AAPCS:

5.2.1.1 Universal stack constraints

  • SP mod 4 = 0. The stack must at all times be aligned to a word boundary

5.2.1.2 Stack constraints at a public interface

  • SP mod 8 = 0. The stack must be double-word aligned.

What is the rational behind 8-byte alignment?

Best Answer

The main reason is that that STRD and LDRD can only work on 8byte aligned addresses. So, to use them on stack variables the stackpointer needs to be 8-byte aligned to all the time.

To quote the ARM Website:

Eight-byte stack alignment is of particular benefit to processors supporting LDRD and STRD instructions, for example, processors based on ARM architecture v5TE and later. If the stack is not eight-byte aligned the use of LDRD and STRD might cause an alignment fault, depending on the target and configuration used.

ARM also explains it in detail in this ABI Advisory Note.

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